1. Field of the Invention
The present invention relates to a high-speed memory device configured to perform bidirectional communication, and more particularly but without limitation, to a high-speed memory device configured to perform bidirectional communication that can be easily tested using the existing low-speed automatic test equipment (ATE) and an input/output pin control method thereof.
2. Description of the Related Art
Recent high-speed semiconductor memory devices have used a bidirectional pulse width modulation (PWM) communication method to control internal registers. A bidirectional communication method is generally referred to as an OOB (Out Of Band) communication method.
FIG. 1 is a schematic diagram of a bidirectional PWM communication system, according to the prior art. FIG. 2A is a waveform diagram illustrating data protocol when data is written to a memory device from a host using the bidirectional PWM communication method, according to the prior art. FIG. 2B is a waveform diagram illustrating data protocol when data is read from the memory device to the host using the bidirectional PWM communication method, according to the prior art.
Referring to FIGS. 1, 2A and 2B, a memory device 200 is coupled to a host 100. The host 100 may be or include, for example, a memory controller. When data “0” is written to the memory device 200, a PMOS pull-up transistor P11 included in the host 100 is turned on for a relatively short period of time to make an OOB bus 12 connected to an OOB pin 11 of the host 100 have a logic high level. Subsequently, an NMOS pull-down transistor N11 included in the host 100 is turned on for a relatively long period of time to make the OOB bus 12 have a logic low level.
When data “1” is written to the memory device 200 from the host 100, the PMOS pull-up transistor P11 of the host 100 is turned on for a relatively long period of time to make the OOB bus 12 become logic high, and then the NMOS pull-down transistor N11 of the host 100 is turned on for a relatively short period of time to make the OOB bus 12 become logic low. When data is written to the memory device 200 from the host 100, a PMOS pull-up transistor P21 included in the memory device 200 is continuously maintained in turned off state.
When data “0” is read from the memory device 200 to the host 100, the PMOS pull-up transistor P11 of the host 100 is turned on for a relatively short period of time such that an OOB bus 12 becomes logic high, and then the NMOS pull-down transistor N11 included in the host 100 is turned on for a relatively long period of time such that the OOB bus 12 becomes logic low. At this time, the PMOS pull-up transistor P21 of the memory device 200 maintains the turned off state.
When data “1” is read from the memory device 200 to the host 100, the PMOS pull-up transistor P11 of the host 100 is turned on for a relatively short period of time such that an OOB bus 12 becomes logic high, and then the NMOS pull-down transistor N11 of the host 100 and the PMOS pull-up transistor P21 of the memory device 200 are turned on for a relatively long period of time. In this case, pull-down strength (current driving capability) of the PMOS pull-up transistor P21 of the memory device 200 is stronger than that of the NMOS pull-down transistor N11 of the host 100, and thus the OOB bus 12 becomes logic high.
FIG. 3 is a schematic diagram of a memory device 200 configured to perform bidirectional PWM communication coupled to Automatic Test Equipment (ATE) 300, according to the prior art. To test the memory device 200, an OOB pin 21 of the memory device 200 is connected to an OOB pin 31 of the ATE 300 through an OOB bus 32. A PMOS pull-up transistor P31, an NMOS pull-down transistor N31 and an input buffer I31 of the ATE 300 respectively correspond to the PMOS pull-up transistor P11, the NMOS pull-down transistor N11 and an input buffer I11 of the host 100 illustrated in FIG. 1.
In the ATE 300, the pull-down strength of the NMOS pull-down transistor N31 is very strong. Accordingly, when data “1” is read from the memory device 200 to the ATE 300, charges of the OOB bus 32 are discharged through the NMOS pull-down transistor N31 of the ATE 300 even when the PMOS pull-up transistor P21 of the memory device 200 is turned on, and thus it is difficult to maintain the OOB bus 32 at logic high.
Furthermore, it is difficult to test the high-speed memory device 200 using the existing low-speed ATE 300.